Method of establishing a master &amp; minus; host in modules connecting in parallel

ABSTRACT

This invention relates to a method of establishing a master unit in a multi-unit parallel system. Each module with a respective number is connected through a bus, and has a different host-identifying pulse width Ts and a host-releasing pulse width Tw. According to the respective numbers, each module sends its host-identifying pulse to the bus and receives the feedback pulse, and then establishes a master unit among all of modules after comparing the feedback pulse width Tr and the host-releasing pulse width Tw. This method effectively realizes a decentralized controlling strategy for phase synchronization in a parallel inverter system and ensures that only one master unit exists in the parallel system. The connection of the multi-string parallel signal bus is simple, and can be connected in circle to provide the redundancy. Compared with the prior art, it is much simple in structure and flexible in configuration and adjustment, and has more reliability and real-time capability.

TECHNICAL FIELD

The present invention relates to the power supply technology. Moreparticularly, it relates to a method for establishing a master unit in amulti-unit parallel system, especially a parallel system composed of aplurality of modules (e.g. inverters) operating in parallel.

BACKGROUND OF THE INVENTION

In a parallel system composed of multiple parallel-connected modules(e.g. inverters), AC outputs from respective inverters are connected inparallel for jointly providing energy for a load so as to improve thecapacity or reliability of the system. To ensure reliable operation ofthe parallel inverter system, the amplitudes of the respective invertersshould be the same and the phases should be synchronized. Otherwise,high circulating current may occur between the parallel-connectedinverters, thereby resulting in overload or damage of the inverters.

In a decentralized parallel inverter system, in order to ensure thephase synchronization among the respective inverters, one of theinverters needs to be set as a master unit while the others act as slaveunits. The master unit can act as the frequency source for the outputvoltage of the entire parallel inverter system, and the slave unitstrack the phase of the output voltage of the master unit. For instance,when the bypass power source fails or goes abnormal in a parallel UPSsystem, every inverter loses the common tracking source. This requiresadopting a control strategy of determining a master and slave units,i.e., establishing only one master unit to maintain the phasesynchronization of all the inverters.

In such a decentralized controlling strategy, it requires one and onlyone master unit employed in the system. The reason is as follows: if nomaster unit exists in the parallel inverter system, each inverter cantrack the output phase of the system and maintain substantially thephase synchronization of the inverters. However, the entire parallelinverter system is in the state of self-excited oscillation such thatthe ultimate output frequency of the system will be diverted from thenominal value. If multiple master units exist in the parallel invertersystem, each master unit serves as the frequency source of the systemand generates output voltage according to the respective nominal values.Since dispersion exists inevitably between the respective nominalfrequency oscillators a significant phase difference will occur overtime in the output voltage of the respective inverters no matter if theinitial state is the same or not, thereby leading to the failure of theparallel connection. In addition, the master unit herein may also beused for time sequential controls in the parallel inverter system.

In the aforesaid phase synchronization strategy, in order to ensure theexistence and uniqueness of the master unit, a number of methods areprovided as follows:

-   (1) The master unit is set manually. A disadvantage of this method    is that it is not flexible. The manually set inverter has to be    turned on before the parallel inverter system operates. While a    fault occurs in the inverter, the parallel inverter system composed    of the rest inverters cannot run properly before a new master unit    is set.-   (2) As illustrated in FIG. 1, the master unit determination relies    on the netlike parallel signal cables laid among the inverters. Any    of the inverters can detect and identify the state of other    inverters. However, a disadvantage of this method is that, due to    the netlike parallel signal connection among the inverters, the    connection cables become complicated when large number of inverters    is used.-   (3) As illustrated in FIG. 2, the master unit determination relies    on the the serial communication among the inverters. The    communication line used between the inverters may be RS485, CAN bus,    etc. However, a drawback of this method lies in the unsatisfied real    time capability and reliability.

In addition to parallel inverter system, the parallel rectifier systemand some master-slave communication system such as RS485 network requireestablishing the master unit as well.

SUMMARY OF THE INVENTION

The technical problem for the present invention to solve is to provide amethod of establishing a master unit in a parallel module system for amulti-module system using a decentralized controlling strategy. Itovercomes the drawbacks of the prior art in establishment of a masterunit, that is, the structural complicacy, inflexibility, lowreliability, complicacy of connection and poor real time capability,etc.

In order to solve the aforesaid technical problems, the presentinvention is to provide a method to establishing a master unit in asystem composed of multiple modules connected in parallel, characterizedin that each module in the parallel system is marked with a respectivenumber and connected by at least one contention bus. The modules withrespective numbers have different host-identifying pulse width Ts andhost releasing pulse width Tw. According to the numbers, each modulesends a corresponding host-identifying pulse width to the contention busunder some condition. At the same time, it receives the feedback pulsefrom the contention bus, and subsequently a master unit is establishedamong all modules by comparing the feedback pulse width Tr and itshost-releasing pulse width Tw.

In the above method of the present invention for establishing a masterunit, the contention bus is a logical OR bus. Each module is initiallydefaulted as a slave unit and sends an invalid low level to thecontention bus.

In the aforesaid method of the present invention for establishing amaster unit, each module sends the host-identifying pulse to thecontention bus to ensure that only one master unit exists in theparallel system. All modules that have not started up or been turned offare initially set as slave units and send invalid low levels to thecontention bus. All modules that have started up send thehost-identifying pulses to the contention bus and detect the feedbackpulse width Tr from the contention bus. If the feedback width Tr issmaller than the host-identifying pulse width Tw of the module, themodule is set as a master unit. If the feedback width Tr is larger thanthe host-identifying pulse width Tw of the module, the module is set asa slave unit.

In the aforesaid method of the present invention for establishing amaster unit, the contention bus comprises a first contention bus and asecond contention bus. Each module is initially defaulted as a slaveunit and sends an invalid low level to both of the contention buses.

In the above method of the present invention having two contention busesfor establishing a master unit, in order to ensure the existence of themaster unit, each module sends a low level to the first and secondcontention bus, including the following steps: all modules that have notstarted up or been turned off are set as slave units, and all of thesemodules that act as slave units send low levels to the first contentionbus, while the module that serves as the master unit sends a high levelto the first contention bus; each module started up detects the feedbacklevel from the first contention bus, and the module is set as a masterunit if the detected feedback level is low; if the detected feedbacklevel is high and the module is still a slave unit, then the moduleremains as a slave unit; if the detected feedback level is high and themodule is already set as a master unit, then the master unit performsthe step to send the host-identifying pulse to the second contention busto ensure that the master unit is unique as described below.

In the aforesaid method of the present invention for establishing amaster unit, the step in which the master unit module sends thehost-identifying pulse to the second contention bus to ensure that themaster unit is unique further comprises: according to its number, themaster unit sends periodically host-identifying pulses to the secondcontention bus; the master unit detects the feedback pulse from thesecond contention bus and records the detected feedback pulse width Trin real time; if the feedback pulse width Tr from the second contentionbus is smaller than the host-removed pulse width Tw of the master unitmodule, then the module remains as the master unit; otherwise, themodule is released from the master state and reset as a slave unit.

In the aforesaid method of the present invention for establishing amaster unit, the first and second contention bus are simple logical ORbuses. At the same time, each module has a first contention logic and asecond contention logic.

In the above-mentioned method of the present invention for establishinga master unit, each module sends a logic level to the first contentionbus by using the first contention logic associated with the firstcontention bus. Each module sends a host-identifying pulse to the secondcontention bus and detects the second contention bus by using the secondcontention logic associated with the second contention bus. The firstcontention logic and the second contention logic can be realized by adigital circuit, such as a trigger based circuits, or a microprocessorand programmable logic device.

In the aforesaid method of the present invention for establishing amaster unit, the number of the module corresponds to a priority. Thehost-identifying pulse width Ts of the module with a high priority islarger than the sum of the host-identifying pulse width Ts of themodules with lower priorities, and is larger than the host-releasingpulse width Tw of any of the modules with lower priorities. Thehost-releasing pulse width Tw of each module other than the one with thehighest priority is larger than the sum of the host-identifying pulsewidth Ts of the module and the host-identifying pulse width Ts of themodules with lower priorities. At the same time, the host-releasingpulse width Tw of a high priority module is larger than thehost-releasing pulse width Tw of the modules with lower priorities.

In the aforesaid method of the present invention for establishing amaster unit, the module established as the master unit can be used tocontrol the frequency source of the output voltage of the entireparallel module system under certain conditions, while the slave unitsother than the one established as master unit may track the outputvoltage phase of the master unit.

Application of the method of the present invention for establishing themaster unit in a parallel module system can be effectively carried outin the above-described phase synchronization strategy of the thirddecentralized control. The method of the present invention forestablishing a master unit in a parallel module systempresents a noveland simple master-slave contention bus such that it can ensure onemaster unit, and only one master unit, exists. In such a master-slavecontention parallel module system, each module has different numbers anda multi-core parallel signal bus is provided therebetween. Unlike thenetlike parallel signal line, the connection of this multi-stringparallel signal bus is simple, and can be connected in circle to provideredundancy. Compared with the prior art, it is much simple in structureand flexible in configuration and adjustment, and has more reliabilityand real-time capability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a parallel module system in the priorart using the master-slave decentralized controlling strategy, in whichthe master unit is determined through the netlike parallel signal lines;

FIG. 2 is an illustrative diagram of a parallel module system in theprior art using the master-slave decentralized controlling strategy, inwhich the master unit is determined through the serial communicationline between the modules;

FIG. 3 is a schematic diagram showing the method for establishing themaster unit in accordance with the parallel module system of the presentinvention;

FIG. 4 is a schematic diagram of the construction of the contentionbuses in accordance with the present invention;

FIG. 5 is a schematic diagram of the contention bus with four modules inaccordance with the first embodiment of the present invention;

FIG. 6 is an illustrative diagram showing the relationship between thetwo host-identifying pulses;

FIG. 7 is a schematic diagram of the construction of the singlecontention bus in accordance with the second and third embodiments ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

The principle of the present invention is illustrated in FIG. 3. Themethod of the present invention is based on a multi-string parallelsignal cable 305 connecting modules 301, 302, 303 and 304. Here invertermodules are taken as an example. In order to establishing a master unit,the application of the method of the present invention is based on themaster-slave contention bus and corresponding master-slave contentionlogic.

As an embodiment of the contention bus of the present invention, themaster-slave contention bus is composed of two logical OR buses in themulti-string parallel signal cable 305 illustrated in FIG. 3, which maybe referred to as a first contention bus 401 and a second contention bus402, as illustrated in FIG. 4. The master-slave contention logic isdisposed in the control logic (not shown) of the respective modules(e.g. inverters) and defined as a first contention logic and a secondcontention logic, which corresponds to the first contention bus 401 andthe second contention bus 402 respectively.

FIG. 5 illustrates the first embodiment of the present invention,wherein the parallel module system comprises four modules. The detailedoperation of the master-slave contention device and the master unitestablishing process are as follows:

-   (1) Initial state: Each module is initially defaulted as a slave    unit and sends an invalid low level to the first contention bus and    the second contention bus.-   (2) The first contention logic of each module is as follows:    -   A. Each module that has not started up or turned off are set as        a slave unit;    -   B. Each slave unit sends a low level to the first contention        bus, while the module that serves as the master unit sends a        high level to the first contention bus;    -   C. Each module that has started up detects the feedback level        from the first contention bus. If the feedback level is low, the        module is set as a master unit. If the feedback level is high        and the module is a slave unit, the module remains as a slave        unit. If the feedback level is high and the module is set as a        master unit, a further process will be performed in accordance        with the second contention logic.-   (3) The second contention logic is as follows:    -   As described above, each module in the parallel module system        has a respective number. According to the numbers, the modules        have two types of characteristic pulses, that is,        host-identifying pulse and host-releasing pulse with the        respective width of Ts and Tw. Both have the period of T. Their        functions are described as follows:    -   A. All slave units send low level to the second contention bus        and the master unit sends periodically host-identifying pulse to        the second contention bus according to its number;    -   B. Each module detects the feedback pulse from the second        contention bus and records the pulse width Tr in real time;    -   C. As described in the first logic, if the feedback level from        the first contention bus detected by the module that has started        up is high and the module is set as a master unit, the second        contention logic process will be performed. Here, if the        feedback pulse width Tr from the second contention bus is        smaller than the host-releasing pulse width of the module Tw,        the module remains as the master unit. Otherwise, it means that        more than one master unit exist in the system and a master unit        having a number with higher priority than the module exists.        Therefore, the module is released from the master state and        reset as a slave unit.

The above-described first and second contention buses supplement witheach other, while the major function of the two buses is somewhatdifferent. So long as there is no master unit in the parallel system atany time, the module that has started up may recognize the situationthrough the first contention bus and set itself as the master unit.However, there may be a possibility that a number of modules start up atthe same time and contend for the master unit simultaneously. Contentionrisk may occur due to the delay of the level signal sent and received onthe first contention bus, thereby creating more than one master unit.Although such a possibility is rare, some measures need to be taken toovercome the defect in consideration of the damage to the parallelsystem that may be caused by multiple master units.

The second contention logic is used to ensure the uniqueness of themaster unit. In case more than one master unit come up in the parallelmodule system, all master units send corresponding host-identifyingpulses to the second contention bus. By detecting the feedback pulsewidth on the second contention bus, the master unit having a number withlower priority will be released from the master state.

In order to ensure the reliability of the aforesaid contention device,the definition of the host-identifying pulse width and thehost-releasing pulse width should comply with certain rules. Take aparallel module system comprising four modules as an example, the numberof each module is 1, 2, 3, and 4, respectively (as shown in FIG. 5). Ifmodule 1 has the highest priority, the host-identifying pulse width andhost-releasing pulse width are provided in the following table (Thetable is intended only as an example and the above pulse width can beselected in a number of ways, wherein the period T of thehost-identifying pulse is assumed as 50 timing units). Module number 1 23 4 Host-Identifying Pulse Width Ts 50 24 12 0 Host-Releasing PulseWidth Tw None 44 18 6

The definition of the host-identifying pulse width satisfies thefollowing relation: 50>=Ts1>Ts2+Ts3+Ts4; Ts2>Ts3+Ts4; Ts3>Ts4.Preferably, the above values may have even intervals therebetween toimprove the ability of anti-interference.

The definition of the host-releasing pulse width satisfies the followingrelation: Tw2>Ts2+Ts3+Ts4; Tw3>Ts3+Ts4; Tw4>Ts4. Preferably, the abovevalues may have even intervals therebetween to improve the ability ofanti-interference.

The reason behind the rules and definitions of the host-identifyingpulse width Ts and the host-releasing pulse width Tw lies in that whenmultiple modules send host-identifying pulses to the second contentionbus at the same time, the pulses may be completely overlapped,completely staggered or partly overlapped since there is no consistentrelationship of synchronization between the pulses from all the modules.

For instance, when modules 2, 3, and 4 are master units at the sametime, module 3 and 4 need to be released from the master state andmodule 2 should remain as the master unit. Here, the host-identifyingpulse width sent to the second contention bus from the modules 2, 3 and4 is 24, 12 and 0, respectively. The feedback pulse width Tr on thesecond contention bus is between 24 (completely overlapped) and 36(completely staggered). According to the second contention logic, thefollowing result can be obtained:

-   -   Module 2: Tr<Tw2 (44), the master state remains    -   Module 3: Tr>Tw3 (18), the master state is released    -   Module 4: Tr>Tw2 (6), the master state is released

As seen above, the result of the contention logic corresponds to thedesired target. Similarly, when the master unit contention risk appearsin other combinations, the master unit establishing process is stillreliable.

In the above embodiment, the master unit contention time isapproximately 0 and the release time is about 50 timing units whenmultiple master units exist.

As the second embodiment (FIG. 7), the above-described master-slavecontention bus is composed of only one logical OR bus in themulti-string parallel signal cable, in which the master-slave logic isas follows:

-   (1) Initial state: Each module is initially defaulted as a slave    unit and sends an invalid low level to the master-slave contention    bus.-   (2) Master-Slave contention logic:    -   Same as in the first embodiment, according to the respective        module numbers, the modules have two types of characteristic        pulse—host-identifying pulse and host-releasing pulse with the        respective width of Ts and Tw. Both have a period of T. In        addition, a fixed master unit existence pulse width Tk is set to        indicate that a master unit exists in the parallel system.    -   A. Each module that has not started up or been turned off are        set as a slave unit;    -   B. The slave unit sends a low level to the contention bus, while        the master unit sends periodically a host-identifying pulse to        the contention bus according to its number;    -   C. Each module constantly detects the feedback pulse width Tr        from the contention bus with a period of T.    -   D. If the module that has started up detects that the feedback        pulse width Tr<=Tk, the module is set as a master unit; if it        detects that the feedback pulse width Tr>Tk and the module is a        slave unit, the module remains as a slave unit; if it detects        that the feedback pulse width Tr>Tk while the module is a master        unit, and if Tr<Tw, the moduleremains as a master unit.        Otherwise, it means that more than one master unit exist in the        system and a master unit having a number with higher priority        than the number of the module exists. Thus, the module is        released from the master state and set as a slave unit.

The master-slave device in the second embodiment can also ensure theexistence and uniqueness of the master unit. Nonetheless, thehost-identifying pulse Ts of each module must be larger than Tk (Tk>0).Take the aforesaid parallel module system comprising four modules as anexample, the host-identifying pulse width and host-releasing pulse widthof each module are provided in the following table (the table isintended only as an example for selecting the above pulse width, whereinT is assumed as 50 timing units and Tk is set at 3 timing units). Modulenumber 1 2 3 4 Host-Identifying Pulse Width Ts 50 24 12 5 Host-ReleasingPulse Width Tw None 46 20 8

The definition of the host-identifying pulse width Ts satisfies thefollowing relation: 50>=Ts1>Ts2+Ts3+Ts4; Ts2>Ts3+Ts4; Ts3>Ts4; Ts4>Tk.Preferably, the above values may have even intervals therebetween toimprove the ability of anti-interference.

The definition of the host-releasing pulse width Tw satisfies thefollowing relation: Tw2>Ts2+Ts3+Ts4; Tw3>Ts3+Ts4; Tw4>Ts4. Preferably,the above values may have even intervals therebetween to improve theability of anti-interference.

Similarly, the definition of the host-identifying pulse width Ts and thehost-releasing pulse width Tw has taken into account the fact thatvarious overlapping situations between the respective pulses may occurwhen each of the modules sends the host-identifying pulse to themaster-slave contention bus at the same time. In the second embodiment,the maximum value of the contention time of the master unit and thereleasing time when multiple master units occur are about 50 timingunits.

In the above-described first embodiment and second embodiment, themaster-slave contention logic comprises a contention process and areleasing process, which is for ensuring the existence and uniqueness ofthe master unit respectively.

In another embodiment in accordance with the present invention, thecontention process and the release process are combined into oneprocess, which can ensure the existence and the uniqueness of the masterunit simultaneously.

Here, the master-slave contention bus is composed of only one logical ORbus in the multi-string parallel signal cable and the master-slave logicis as follows:

-   (1) Initial state: Each module is initially defaulted as a slave    unit.-   (2) Master-Slave contention logic:    Similarly, according to the respective module numbers, the modules    have two types of characteristic pulses—host-identifying pulse and    host-releasing pulse with the respective width of Ts and Tw. Both    have a period of T.    -   A. All modules that have not started up send invalid low levels        to the master-slave contention bus and are set as slave units;    -   B. Each started module sends host-identifying pulse to the        master-slave contention bus;    -   C. Each module constantly detects the feedback pulse width Tr        from the master-slave contention bus at a period of T. If the        feedback pulse Tr is less than its host-releasing pulse Tw, the        module is set as a master unit. If the feedback pulse Tr is        larger than its host-releasing pulse Tw, the module is set as a        slave unit.

In order to ensure the reliability of the aforesaid contention device,the definition of the host-identifying pulse width and thehost-releasing pulse width should comply with certain rules. Take aparallel module system comprising four modules as an example, the numberof each module is 1, 2, 3, and 4 respectively. If module 1 has thehighest priority, the host-identifying pulse width and host-releasingpulse width are provided in the following table (the table is intendedonly as an example and the above pulse width can be selected in a numberof ways, wherein the period T of the host-identifying pulse is assumedas 50 timing units). Module number 1 2 3 4 Host-Identifying Pulse WidthTs 48 24 12 4 Host-Releasing Pulse Width Tw 52 44 20 8

The definition of the host-identifying pulse width Ts satisfies thefollowing relation: Ts1>Ts2+Ts3+Ts4; Ts2>Ts3+Ts4; Ts3>Ts4. Preferably,the above values may have even intervals therebetween to improve theability of anti-interference.

The definition of the host-releasing pulse width Tw satisfies thefollowing relation: Tw1>Ts1 +Ts2+Ts3+Ts4; Ts1>Tw2>Ts2+Ts3+Ts4;Ts2>Tw3>Ts Ts3>Tw4>Ts4. Preferably, the above values may have evenintervals therebetween to improve the ability of anti-interference.

Here, the definition of the host-identifying pulse width Ts and thehost-releasing pulse width also take into account the possiblesituations of complete overlapping, complete staggering or partlyoverlapping of the pulses, which may occur when more than one modulessend the host-identified pulse to the master-slave contention bus at thesame time. In this embodiment, both the maximum value of contention timeof the master unit and the releasing time when the multiple master unitsexist are about 50 timing units. However, the difference lies in thatthe module that starts up late having a number with higher priority maypreempt the master state of the module that starts up earlier having anumber with lower priority.

The master-slave contention device can be realized by the digitalcircuit, such as triggers based circuits, or microprocessor andprogrammable logic device, wherein the master-slave contention bus maybe a simple OR structure or modified logical OR structure, and may alsorepresent as AND logic structure in a negative logic method.

The application of the master-slave contention device in accordance withthe present invention should not be limited to the parallel modulesystem, and may cover other decentralized parallel systems. Each moduleof the parallel module system is characterized by having their outputsconnected together, such as the modules in the parallel UPS system. Themaster unit can control the frequency source of the output voltage ofthe entire parallel module system under certain conditions, and theslave units track the phase of the output voltage of the master unit.The master unit can also be used for the time sequential control and thesynchronization of switching periods of the parallel module system, etc.

1. A method for establishing a master unit in a parallel systemincluding multiple modules connected in parallel, characterized in thateach module in said parallel system is marked with a respective numberand connected through at least one contention bus, wherein the moduleswith said respective numbers have different host-identifying pulse width(Ts) and host releasing pulse width (Tw); each of said modules sendingthe corresponding host-identifying pulse to said contention busaccording to its number and receiving a feedback pulse from saidcontention bus at the same time; and one of said modules beingestablished as a master unit by comparing its received feedback pulsewidth (Tr) with its host-releasing pulse width (Tw).
 2. The method ofclaim 1, characterized in that said contention bus is a logic OR bus,each of said modules being initially defaulted as a slave unit, and eachof said modules sending an invalid low level to said contention bus. 3.The method of claim 2, characterizedin that each of said modules sends ahost-identifying pulse to said contention bus to ensure the uniquenessof the master unit, comprising the following steps: setting any of themodules that has not started or been turned off as a slave unit; themodule that has started sending its host-identifying pulse to saidcontention bus and detecting the feedback pulse width (Tr); setting themodule as master unit if the feedback pulse width (Tr) is smaller thanits host-releasing pulse width (Tw); and setting the module as the slaveunit if the feedback pulse width (Tr) is larger than its host-releasingpulse width (Tw).
 4. The method of claim 1, characterized in that saidcontention bus comprises a first contention bus and a second contentionbus, each of said modules being initially defaulted as a slave unit, andeach of said modules sending an invalid low level to said first andsecond contention buses.
 5. The method of claim 4, characterized in thateach of said modules sends a low level to the first contention bus inorder to ensure the existence of the master unit, comprising thefollowing steps: setting any of the modules that has not started up orbeen turned off as a slave unit; all the modules that act as slave unitssending low levels to said first contention bus, while the module thatserves as the master unit sending a high level to said first contentionbus; each of said modules that has started detecting the feedback pulsefrom said first contention bus, and setting the module as the masterunit if the feedback level is low; maintaining the module as the slaveunit if the feedback level is high and the module is a slave unit; ifthe feedback level is high and the module is set as a master unit, eachof said modules performing a further step to send the correspondinghost-identifying pulse to the second contention bus to ensure that themaster unit is unique.
 6. The method of claim 5, characterized in thateach of said modules sends its host-identifying pulse to the secondcontention bus in order to ensure the uniqueness of the master unit,comprising the following steps: all of the modules that act as slaveunits sending low levels to said second contention bus, while the modulethat serves as the master unit sending a periodical host-identifyingpulse to said second contention bus according to its number; each ofsaid modules detecting the feedback pulse from said second contentionbus and recording the feedback pulse width (Tr) in real time; if thefeedback level from said first contention bus detected by said eachmodule is high and the module is set as a master unit, and if thefeedback pulse width (Tr) from the second contention bus is smaller thanthe host-releasing pulse width (Tw) of the module, maintaining themodule as the master unit; otherwise releasing the module from themaster state and setting the module as a slave unit.
 7. The method ofclaim 6, characterized in that said first contention bus and said secondcontention bus are simple logic OR bus or simple AND bus.
 8. The methodof claim 7, characterized in that each of said modules sends logic levelto said first contention bus by using a first contention logicassociated with said first contention bus; each of said modules sendsthe host-identifying pulse to said second contention bus and detectssaid second contention bus by using a second contention logic associatedwith said second contention bus; said first contention logic and saidsecond contention logic can be realized by a digital circuits, such as atrigger based circuits, or a microprocessor and programmable logicdevice.
 9. The method of any of claim 1-8, characterized in that thenumber of each of said modules corresponds to a priority; thehost-identifying pulse width (Ts) of the module with a high priority islarger than the sum of the host-identifying pulse width (Ts) of themodules with lower priorities, and is larger than the host-releasingpulse width (Tw) of any of the modules with a lower priority; thehost-releasing pulse width (Tw) of each module other than the one withthe highest priority is larger than the host-identifying pulse width(Ts) of the module, at the same time, the host-releasing pulse width(Tw) is larger than the host-releasing pulse width (Tw) of the moduleswith lower priorities.